library verilog;
use verilog.vl_types.all;
entity ctr_seq is
    port(
        curstate        : out    vl_logic_vector(2 downto 0);
        nextstate       : in     vl_logic_vector(2 downto 0);
        clk             : in     vl_logic;
        rst             : in     vl_logic
    );
end ctr_seq;
